1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a semiconductor device that affords a highly reliable connection to an external substrate.
2. Description of the Related Art
In recent years, in keeping with the miniaturization of semiconductor devices, a semiconductor device package structure known as a Chip Size Package (hereinafter referred to as a ‘CSP’) the outer dimensions of which are substantially the same as the outer dimensions of the semiconductor chip has emerged. One form of CSP is a semiconductor device package structure known as a Wafer Level Chip Size Package (hereinafter referred to as a ‘WCSP’) in which packaging is performed in a wafer state.
A semiconductor device having this WCSP structure will be described below.
In a conventional WCSP structure semiconductor device, electrodes are formed on a semiconductor chip on which an integrated circuit is already formed. An insulation film is formed on the semiconductor chip so that the top faces (upper surfaces) of the electrodes are exposed. The insulation film has a plurality of openings and the top faces of the electrodes are exposed by these openings.
Wiring and terminals known as posts are formed on the insulation film. Normally, this wiring is known as rewiring or relocated wiring, and one end of the wiring is connected to the electrodes via the openings in the insulation film, while the other end is connected to the posts.
In addition, the top side of the semiconductor device is sealed by means of a sealing material such as resin so that the top faces of the posts are exposed, and an external terminal such as a solder ball is formed on the top face of each of the exposed posts.
This WCSP structure packaging is undertaken in a wafer state. Wafers are cut and divided up after being sealed, whereby many CSP-structure semiconductor chips are produced.
However, if a temperature change or similar is applied after the WCSP-structure semiconductor device has been mounted on an external substrate or the like, stress acts on the external terminals because the thermal expansion rate of the semiconductor device is greatly different from the thermal expansion rate of the external substrate. As a result, there may be concentration of stress at the join between the top face of the posts and the external terminals, and cracks will be generated at the join.
In addition, if a semiconductor device is mounted in a portable device such as a cellular phone, and the semiconductor device is carried round, the semiconductor device is often subjected to the collisions and vibrations and stress acts on the external terminals. Thus, there is the possibility that there will be a concentration of stress at the join between the top face of the post and the associated external terminal. This concentration of the stress cracks the joint.
As a result, there is the possibility that the joining forces between the posts and the external terminals will drop and that there will be a large reduction in the reliability of the connection between the semiconductor device and the external substrate.
A technology that is intended to resolve this problem is disclosed in, for example, Japanese Patent Application Kokai (Laid Open Publication) No. 2000-353766. This involves exposing the side of each post by removing the sealing material on the circumference of each post by irradiating the sealing material with a laser, and then forming an external terminal on the side of the exposed post and on the top face of the post.
In the connection structure disclosed in Japanese Patent Application Kokai No. 2000-353766, the stress acting on each external terminal can be dispersed at the side and top face of the associated post, whereby the possibility of a concentration of stress at the join between the top face of the post and the associated external terminal can be reduced-and hence the reliability of the connection between the semiconductor device and the external substrate can be raised.
However, with the technology disclosed in Japanese Patent Application Kokai No. 2000-353766, because the step of removing the sealing layer from the circumference of each of the posts by means of a laser takes an extremely long time, the package fabrication time increases and a drop in production efficiency occurs.